(1) Field of the Invention
The present invention relates to an integrated standard cell in which the layout of clock signal lines has been improved.
(2) Description of the Prior Art
As one development approach to Custom LSIs, a standard cell system has been heretofore proposed. In this system, desired LSIs can be realized by placement and routing of functional blocks (which are referred to hereunder as "cells") such as simple logical gates and flip-flops (F/Fs) which are preliminarily prepared including the power supply lines and ground lines.
FIG. 1 shows one example of the F/F circuit construction as a standard cell. The functional block comprises F/F section 1 which functions as a flop-flop and a clock signal generating section 3 for supplying clock signals .phi., .phi. to the F/F section 1. In addition, a power supply wiring 5 shown by VDD and a ground wiring 7 shown by GND are formed so as to sandwich the F/F section 1 and the clock signal generating section 3.
Data as an input signal is applied to the F/F section 1 from the outside of the cell through a data line 9, VIA 11 and a contact hole 13. On the other hand, a reference clock signal as an input signal is supplied to the clock signal generating section 3 from the outside of the cell through a clock signal line 15, VIA 11, and another contact hole 13.
FIG. 2 shows one cell portion 17 in which data is applied to the cell 17 through a data line 19 made of, for instance, first Al layer and a successive line 21 made of a second Al layer which are connected by the VIA 11 which forms a metal wiring junction. On the other hand, the reference clock signal as well is applied to the cell through a clock signal line 23 made of a first Al layer and a succesive line 25 made of a second Al layer, connected by the VIA 11, similar to the data signal line.
These cells described above are arranged and wired by using an automatic placement and routing program as shown in FIG. 3. Namely, each of the cells 27, having substantially same height but having different width respectively is arranged so as to contact in the direction of the length of the cells or in the row direction. Each group of the contacted cells in the row direction is arranged in the column direction to have a space therebetween and the space is used for forming a wire.
Since each of the power supply lines and each of the ground lines are formed in each cell, the power supply line and the ground line of the adjacent cells can be automatically connected when the automatic placement and routing technique is applied. As a result, the power supply line and the ground line of the cells arranged in a same row are duly connected at the same time when the automatic arranging and wiring of the cells are carried out.
Whilst data lines and clock lines are connected by a multiple of VIAs 11, 11 in the areas sandwiched by two rows of cells as shown in FIG. 3, so as to supply data or clock signals to each cell. It is to be noted from the above description that the clock signal lines have been wired in accordance with the same design rules as those of the data lines in the automatic placement and routing technique, with the standard cells according to the prior art being used.
FIG. 4 shows an equivalent circuit of the clock signal line consisting of stray capacitors C, C which exist in the line and resistors R, R which represents the resistances of the line and the VIA 11. These capacitors and resistors cause a time delay or skew in the reference clock signal between the start point and the end point of the line, as shown in FIG. 4. This skew in the reference clock signal results in a malfunction of the cells to which the reference clock signal is supplied. In addition, the effect of the skew becomes significant as the frequency of the clock signal increases.
Accordingly, some countermeasures for the skew of the clock signal are required. When the clock signal lines are drawn here and there as shown in FIG. 3, however, it becomes difficult to predict each wiring length and the number of VIAs. This is turn results in the difficulty of accurately estimating the stray capacitors and the resistors, which is related to the skew problem.
Moreover, when the standard cell requires two kinds of the clock signals .phi. and .phi. (its inverted clock signal) and these signals .phi., .phi. are supplied independently from outside, a skew occurs between the clock signals .phi. and .phi.. In order to avoid this skew problem, it is necessary to generate within the cell, the clock signals .phi., .phi. from the reference clock signal. However, when trying to do so, it becomes necessary to provide a clock generating circuit for every cell which requires two clock signals .phi., .phi.. Consequently, as the generated clock signals must be provided to logical circuits which require these two clock signals within the cell, additional area for clock wiring is required for the individual standard cells, which becomes a bar to high circuit integration.